Description V-11

1 description

1.1 rom/ram chip
1.2 i/e chip
1.3 m chip
1.4 f chip
1.5 cache
1.6 physical

description

the v-11 multichip design, consisting of i/e chip, m chip, f chip , 5 rom/ram chips. unlike microvax 78032, implemented subset of vax isa, v-11 complete vax implementation, supporting of 304 instructions , 17 data types (byte, word, longword, quadword, octaword, f-floating, d-floating, g-floating, h-floating, bit, variable-length bit field, character string, trailing numeric string, leading separate numeric string, packed decimal string, absolute queue, , self-relative queue).

the chips in chip set connected 4 buses: mib, dal, pal , cal. mib (microinstruction bus) carried microinstructions control signals , addresses control store i/e , f chips. mib 40 bits wide, same width microword , parity protected. dal 32-bit parity-protected bus carries data addresses , i/e, m , f chips, cache, backup translation buffer rams , port interface.

rom/ram chip

the rom/ram chip (dc327) implemented one-fifth of patchable control store. contained 16,384 8-bit (16 kb) read-only memory (rom), 1,024 8-bit (1 kb) random-access memory ram , 32 14-bit content-addressable memory (cam). rom contained control store, ram used hold control store patches. rom/ram consisted of 208,000 transistors on die measuring 344 mils 285 mils (8.74 mm 7.24 mm) area of 98,040 mil (63.25 mm). dissipated 1 w.

i/e chip

the i/e chip (dc328) contained instruction buffer, microsequencer, execution unit , mini-translation buffer (mtb). instruction buffer two-entry 32-bit buffer held prefetched instructions. improved performance maintaining number of instructions ready execution. hardware attempted keep instruction buffer full @ times. execution unit consisted of sixteen 32-bit general purpose registers defined vax isa, arithmetic logic unit (alu) , shifter. mtb translation lookaside buffer (tlb). contained 5 page table entries (ptes), 1 instruction , 4 data. in event of miss, backup translation buffer (btb) in m chip used. i/e chip consisted of 60,000 transistors on die measuring 354 mils 358 mils (8.99 mm 9.09 mm) area of 126,732 mil (81.76 mm). dissipated 5 w.

m chip

the m chip (dc329) responsible memory management , interrupt handling. contained backup translation buffer (btb) tags, cache tags , internal processor registers. m chip contained i/o functionality defined vax architecture , generated clock signal chip set.

the backup translation buffer translation lookaside buffer (tlb) handled miss in mtb. btb contained 512 page table entries (ptes), of 256 system-space pages , 256 process-space pages. there 128 btb tags, 1 every 4 ptes, located in m chip. btb implemented external rams.

there 26 internal processor registers, used microcode temporary storage when executing complex instructions requiring multiple cycles.

the m chip consisted of 54,000 transistors on die measuring 339 mil 332 mil (8.61 mm 8.43 mm) area of 112,548 mil (72.61 mm). dissipated 3 w.

f chip

the f chip (dc330) contained floating-point unit (fpu). supported vax floating-point instructions , f_floating, d_floating , g_floating data types defined in vax architecture , responsible executing integer divide , multiply instructions. f chip received opcodes i/e chip , microinstructions control store on mib bus. operands received memory or general purpose registers on dal bus, used write results. consisted of 29,600 transistors on 341 mil 288 mil die (8.66 mm 7.32 mm) area of 98,208 mil (63.36 mm). dissipated 2.5 w.

the f chip derivative of fpa, belonged j-11 microprocessor chip set, implementation of pdp-11. f chip supposed new design developed v-11, cancelled in favor of derivative part of effort simplify v-11 completed quicker development of microvax 78032 had begun.

cache

the v-11 has external 8 kb primary cache. cache physically addressed , has 64-byte cache block.

physical

the v-11 chip set contained total of 1,183,600 transistors spread on 9 dies fabricated in digital s zmos process, 3.0 µm nmos process 2 levels of interconnect.